The present invention relates to an internal voltage generator and a semiconductor memory device including the same.
A variety of semiconductor devices generate and use a variety of internal voltages that are different in level from an external supply voltage. In particular, a semiconductor memory device generates a variety of reference voltages VREF that are used as a reference for a circuit operation, a voltage VCORE that is used in a core region of the memory device, a voltage VPP that is higher than an external voltage applied to a word line or a gate of a cell transistor, and a voltage VBB that is lower than a ground voltage used in a bulk of a cell transistor.
FIG. 1 is a block diagram of a conventional circuit for generating a reference voltage VREF.
Referring to FIG. 1, a conventional reference voltage generator circuit includes a band gap unit 110 and a voltage divider 120.
The band gap unit 110 generates a band gap voltage VGB with a predetermined level in response to a change in PVT (Process, Voltage and Temperature). The voltage divider 120 generates an internal voltage VREF using the band gap voltage VBG. The band gap unit 110 and the voltage divider 120 will be described in detail with reference to FIGS. 2 and 3.
FIG. 2 is a circuit diagram of the band gap unit 110 illustrated in FIG. 1.
Referring to FIG. 2, the band gap unit 110 is implemented using a vertical PNP BJT transistor that is small in terms of a process change. This includes a combination of a Proportional to Absolute Temperature (PTAT) term, which causes the amount of current to increase with temperature, and a Complementary proportional to Absolute Temperature (CTAT) term, which causes the current flow to decrease with temperature.
On the assumption that a node A and a node B are virtually shorted in the circuit, a general diode current-voltage relationship, which is represented by an emitter current of two BJTs Q1 and Q2 with a ratio of N:1, can be expressed as Equation (1).IQ=IS(exp[VBE/VT]−1)≈ISexp[VBE/VT]VBE>>VT  (1)
Applying this to Q1 and Q2 results in Equation (2)IQ1=ISexp[VBE1/VT],IQ2=ISexp[VBE2/VT]  (2)where IQ1 denotes a current flowing through the first BJT, and IQ2 denotes a current flowing through the second BJT.
If the node A and the node B have the same potential, a current IPTAT flowing through a first resistor R1 can be expressed as Equation (3).IPTAT=(VBE1−VBE2)/R1=ln(N·α)·VT/R1  (3)
Under the same condition, a current ICTAT flowing through a second resistor R2 can be expressed as Equation (4).ICTAT=VBE1/R2  (4)
On the assumption that the same amount of current flows through MOSs of the same size, a current M*IPTAT and a current K*ICTAT respectively become M*IPTAT and K*ICTAT as illustrated in FIG. 2.
Based on this, an output voltage VBG of the band gap unit 110 can be expressed as Equation (5).VBG=K·R1/R2·(VBE1+(M·R1/K·R1)·ln(N·α)·VT)  (5)
If the values M, R1, R2, R3, K and M are suitably adjusted for temperature compensation, the output voltage VBG has a constant value regardless of a PVT change. In general, if the current amounts PTAT and CTAT are adjusted by adjusting only the values K and M while fixing the values N, R1, R2 and R3.
That is, the band gap unit 110 outputs a voltage VBG that has a constant value regardless of a PVT change.
FIG. 3 is a circuit diagram of the voltage divider 120 illustrated in FIG. 1.
Referring to FIG. 3, the voltage divider 120 includes an OP amplifier 310, a PMOS transistor 320, and resistors 330 and 340.
In operation, the output voltage VBG of the band gap unit 110 is input into the OP amplifier 310 and then the output of the OP amplifier 310 is input into a gate of the PMOS transistor 320 to drive the PMOS transistor 320. As a result, the voltage levels of both inputs of the OP amplifier 310 become identical to each other. That is, the potential level of a node C becomes VBG.
The voltage VBG of the node C is voltage-divided by the resistors 330 and 340. Thus, according to the resistance ratio, an internal voltage VREF={VBG*(Resistance 340+Resistance 330)/Resistance 340}.
The level of the internal voltage VREF, which is generated through the above operation, does not easily change even in case of a PVT change. Therefore, the internal voltage VREF is used as a reference voltage for various circuits in a semiconductor device. The internal voltage VREF may also be used as a reference voltage for generating the other internal voltages (e.g., VCORE, VBB and VPP), where the level of the reference voltage differs depending on the type of the internal voltage.
FIG. 4 is a block diagram of a conventional circuit for generating a negative voltage VBB that has a lower level than a ground voltage VSS.
Referring to FIG. 4, a conventional negative voltage generator circuit includes: a negative voltage detector 410 configured to detect the level of a negative voltage VBB and to output a pump enable signal BBWEB if the level of the negative voltage VBB is not sufficiently low; and a negative voltage pump 420 configured to pump the negative voltage VBB in response to the pump enable signal BBWEB output from the negative voltage detector 410.
The negative voltage detector 410 detects the level of a negative voltage VBB, and outputs a pump enable signal BBWEB that is used to determine whether to drive the negative voltage pump 420. The negative voltage pump 420 pumps the negative voltage VBB in response to the pump enable signal BBWEB output from the negative voltage detector 410. The negative voltage pump 420 includes oscillator 421, a pump controller 422, and a charge pump 423.
The oscillator 421 receives the pump enable signal BBWEB and outputs a periodic signal OSC. The pump controller 422 outputs pump control signals P1, P2, G1 and G2 in response to the periodic signal OSC output from the oscillator 421. The charge pump 423 outputs a negative voltage VBB in response to the pump control signals P1, P2, G1 and G2 output from the pump controller 422.
In the overall operation, if the level of the negative voltage VBB detected by the negative voltage detector 410 is sufficiently low (i.e., BBWEB Disable), the negative voltage pump 420 stops a pumping operation. On the other hand, if the level of the negative voltage VBB detected by the negative voltage detector 410 is not sufficiently low (i.e., BBWEB Enable), the negative voltage pump 420 performs a pumping operation.
FIG. 5 is a circuit diagram of the negative voltage detector 410 illustrated in FIG. 4.
Referring to FIG. 5, a ground voltage VSS is applied to a gate of a first transistor P01, and a negative voltage VBB is applied to a gate of a second transistor P02. The transistors P01 and P02 operate in a linear region, and serve as resistors to divide a high-potential voltage VREFB and a low-potential voltage VSS. For example, if the absolute value of the negative voltage VBB is small (i.e., if the level of the negative voltage VBB is high) and thus the resistance of the second transistor P02 increases, the voltage level of a node DET increases and thus a third inverter 103 outputs a low-level detection signal BBWEB (i.e., the negative voltage VBB is pumped). On the other hand, if the absolute value of the negative voltage VBB is large (i.e., if the level of the negative voltage VBB is low) and thus the resistance of the second transistor P02 decreases, the voltage level of the node DET decreases and thus the third inverter 103 outputs a high-level detection signal BBWEB (i.e., the negative voltage pumping operation is stopped).
That is, the negative voltage detector 410 detects the level of the negative voltage VBB by the voltage division of the transistors P01 and P02 that respectively receive the ground voltage VSS and the negative voltage VBB.
For reference, FIG. 5 exemplifies VREFB as a high-potential voltage, which can be obtained using a reference voltage generator circuit as illustrated in FIG. 1. This, however, is merely exemplary, and a variety of other voltages (e.g., VCORE and VDD) may be used.
FIG. 6 is a detailed circuit diagram of the oscillator 421 illustrated in FIG. 4.
Referring to FIG. 6, the oscillator 421 may be configured in the shape of a ring oscillator that includes a NOR gate 601 receiving the pump enable signal BBWEB and inverters 602 to 607.
If the ‘high’ pump enable signal BBWEB is input into the NOR gate 601, the NOR gate 601 outputs a ‘low’ signal. On the other hand, if the ‘low’ pump enable signal BBWEB is input into the NOR gate 601, the NOR gate 601 serves as an inverter. Thus, the oscillator 421 outputs a periodic signal OSC through the inverters 602 to 607.
FIG. 7 is a circuit diagram of the pump controller 422 illustrated in FIG. 4. FIG. 8 is an operation timing diagram of the pump controller 422 illustrated in FIG. 4.
Referring to FIGS. 7 and 8, the pump controller 422 includes a plurality of NAND gates and a plurality of inverters, and outputs the control signals P1, P2, G1 and G2 that are used to control the charge pump 423. The control signals P1 and P2 are used to enable a pumping operation of the charge pump 423, and the control signals G1 and G2 are a kind of precharge signal.
FIG. 9 is a circuit diagram of the charge pump 423 illustrated in FIG. 4.
Referring to FIG. 9, the charge pump 423 serves to generate the negative voltage VBB trough a charge pumping operation. The charge pump 423 includes PMOS transistors 901, 902, 903 and 904. The PMOS transistor 901 operates as a capacitor in response to the control signal P1 that is applied to a node to which its source and drain are connected. The PMOS transistor 902 operates as a capacitor in response to the control signal P2 that is applied to a node to which its source and drain are connected. The PMOS transistor 903 operates as a capacitor in response to the control signal G1 that is applied to a node to which its source and drain are connected. The PMOS transistor 904 operates as a capacitor in response to the control signal G2 that is applied to a node to which its source and drain are connected.
In operation, the control signals P1 and P2 are applied to pump the negative voltage VBB, and the control signals G1 and G2 are applied to change the potential of nodes ‘a’ and ‘b’ into the ground voltage VSS.
FIG. 10 is a block diagram of a conventional circuit for generating a high voltage VPP that is higher than a supply voltage VDD.
Referring to FIG. 10, a conventional high voltage generator circuit includes: a high voltage detector 1010 configured to detect the level of a high voltage VPP and to output a pump enable signal PPES if the level of the high voltage VPP is not sufficiently low; and a high voltage pump 1020 configured to pump the high voltage VPP in response to the pump enable signal PPES output from the high voltage detector 1010.
The high voltage detector 1010 detects the level of a high voltage VPP, and outputs a pump enable signal PPES that is used to determine whether to drive the high voltage pump 1020. The high voltage pump 1020 pumps the high voltage VPP in response to the pump enable signal PPES output from the high voltage detector 1010. The high voltage pump 1020 includes oscillator 1021, a pump controller 1022, and a charge pump 1023.
The oscillator 1021 receives the pump enable signal PPES and outputs a periodic signal OSC. The pump controller 1022 outputs pump control signals P1, P2, G1 and G2 in response to the periodic signal OSC output from the oscillator 1021. The charge pump 1023 outputs a high voltage VPP in response to the pump control signals P1, P2, G1 and G2 output from the pump controller 1022.
In the overall operation, if the level of the high voltage VPP detected by the high voltage detector 1010 is sufficiently high (i.e., PPES Disable), the high voltage pump 1020 stops a pumping operation. On the other hand, if the level of the high voltage VPP detected by the high voltage detector 1010 is low (i.e., PPES Enable), the high voltage pump 1020 pumps the high voltage VPP.
The high voltage generator circuit of FIG. 10 generates the high voltage VPP through a charge pumping operation and thus is similar to the negative voltage generator circuit of FIG. 4 in terms of operation and configuration.
FIG. 11 is a circuit diagram of the high voltage detector 1010 illustrated in FIG. 10.
Referring to FIG. 11, the high voltage detector 1010 divides the high voltage VPP fed back from the charge pump 1023, and detects the level of the high voltage VPP through comparison with a reference voltage VREFP. If the level of the high voltage VPP decreases below a target level, the voltage level of a node C decreases below the reference voltage VREFP. Then, a transistor N02 forming a current mirror is turned on more strongly than a transistor N01, so that the logic level of a node D becomes ‘low’. Thus, an inverter 1101 outputs the high-level pump enable signal PPES, so that the high voltage VPP is pumped.
On the other hand, if the level of the high voltage VPP is higher than the target level, the voltage level of the node C becomes higher than the reference voltage VREFP. In this case, the logic level of a node D becomes ‘high’. Thus, the inverter 1101 outputs the low-level pump enable signal PPES, so that the high voltage pumping operation is stopped.
The reference voltage VREFP may be generated using a reference voltage generator circuit as illustrated in FIG. 1. The reference voltage VREFP may also be generated using other techniques, for example, by voltage division of the supply voltage VDD.
FIG. 12 is a detailed circuit diagram of the oscillator 1021 illustrated in FIG. 10.
Referring to FIG. 12, the oscillator 1021 may be configured in the shape of a ring oscillator that includes a NAND gate 1201 receiving the pump enable signal PPES and inverters 1202 to 1207. Both of the oscillator 1021 of FIG. 12 and the oscillator 421 of FIG. 6 have the shape of a ring oscillator. However, since the pump enable signal PPES is activated to ‘high’ unlike the pump enable signal BBWEB, the oscillator 1021 uses the NAND gate 1201 instead of the NOR gate 601.
If the ‘low’ pump enable signal PPES is input into the NAND gate 1201, the NAND gate 1201 outputs a ‘low’ signal. On the other hand, if the ‘high’ pump enable signal PPES is input into the NAND gate 1201, the NAND gate 1201 serves as an inverter. Thus, the oscillator 1021 outputs a periodic signal OSC through the inverters 1202 to 1207.
FIG. 13 is a circuit diagram of the pump controller 1022 illustrated in FIG. 10. FIG. 14 is an operation timing diagram of the pump controller 1022 illustrated in FIG. 10.
Referring to FIGS. 13 and 14, the pump controller 1022 includes a plurality of NAND gates and a plurality of inverters, and outputs the control signals P1, P2, G1 and G2 that are used to control the charge pump 1023. The control signals P1 and P2 are used to enable a pumping operation of the charge pump 1023, and the control signals G1 and G2 are a kind of precharge signal.
The timing of generating the control signals P1, P2, G1 and G2 according to the periodic signal OSC is illustrated in FIG. 14, and the timing of FIG. 14 is slightly different from the timing of FIG. 8 because not the negative voltage VBB but the high voltage VPP is pumped.
FIG. 15 is a circuit diagram of the charge pump 1023 illustrated in FIG. 10.
Referring to FIG. 15, the charge pump 1023 serves to pump the high voltage VPP. The charge pump 1023 includes NMOS transistors 901, 902, 903 and 904. The NMOS transistor 1501 operates as a capacitor in response to the control signal P1 that is applied to a node to which its source and drain are connected. The NMOS transistor 1502 operates as a capacitor in response to the control signal P2 that is applied to a node to which its source and drain are connected. The NMOS transistor 1503 operates as a capacitor in response to the control signal G1 that is applied to a node to which its source and drain are connected. The NMOS transistor 1504 operates as a capacitor in response to the control signal G2 that is applied to a node to which its source and drain are connected.
In operation, the control signals P1 and P2 are applied to pump the high voltage VPP, and the control signals G1 and G2 are applied to change the potential of nodes ‘e’ and ‘f’ into the ground voltage VSS.
FIG. 16 is a circuit diagram of a conventional internal voltage generator circuit using a down-converting technique.
An example of an internal voltage generated using a down-converting technique is a core voltage VCORE used in a core region of a semiconductor memory device. Hereinafter, a description will be given of a core voltage (VCORE0 generator circuit.
Referring to FIG. 16, a conventional core voltage generator circuit includes a differential amplifier 1610, a driver 1620, and a voltage divider 1630. The differential amplifier 1610 is configured to receive a fed-back core voltage VCORE_FEED and a reference voltage VREFC to output a driver control signal DET. The driver 1620 is configured to drive a core voltage VCORE in response to the driver control signal DET. The voltage divider 1630 is configured to divide the core voltage VCORE to generate the fed-back core voltage VCORE_FEED.
As illustrated in FIG. 16, the differential amplifier 1610 may be constructed to include an operational amplifier (OP Amp). The driver 1620 may be constructed to include a PMOS transistor that drives the core voltage VCORE in response to the driver control signal DET. The voltage divider 1630 may be constructed to include diode-connected transistors that divide the core voltage VCORE to generate the fed-back core voltage VCORE_FEED.
When the circuit starts to operate, both terminals of the differential amplifier 1610 has the same voltage and thus VCORE_FEED=VREFC. Then, a voltage, which is higher than the reference voltage VREFC and lower than a supply voltage VDD, is output as the core voltage VCORE depending on the resistance ratio of the diode-connected transistors.
A variety of internal voltage generator circuits described above are used in a variety of semiconductor devices to generate internal voltages that are different in level from the supply voltage.
After manufactured, a semiconductor device does not operate at only one speed. The operation speed (e.g., clock frequency) of a semiconductor device may vary depending on the type of a system using the semiconductor device. Moreover, the operation speed of a semiconductor device may vary according to circumstances even when the semiconductor device is used in one system.
The power consumption of a semiconductor device differs depending on the operation speed of the semiconductor device. In general, the power consumption of a semiconductor device increases with an increase in the operation speed of the semiconductor device, and decreases with a decrease in the operation speed of the semiconductor device. Thus, the levels of the internal voltages used in a semiconductor device needs to be changed depending on the operation speed of the semiconductor device.
For example, the power consumption of a semiconductor device increases as the clock frequency of the semiconductor device increases. In this case, the level of an internal voltage decreases as the operation speed of the semiconductor device increases. The reason for this is that the stable power for an internal voltage generator circuit is difficult to achieve and the internal voltage is consumed more rapidly. This causes a timing loss in various circuits such as a bit line sense amplifier (BLSA), an input/output sense amplifier (IOSA), and a write driver that are sensitively affected by the on/off time of a transistor due to an internal voltage in a core region.